An example of an overall arrangement of a conventional light-modulating detecting device will be schematically explained with reference to FIGS. 4 and 5. As shown in FIG. 4, a light-emitting element 34 is driven to perform pulse-modulation through an oscillation circuit 31 and a light-emitting element drive circuit 33. The light-emitting element 34 projects pulse-modulated pulse light toward an object S that exists in a detection area (not shown).
The pulse-modulated pulse light is transmitted through or is reflected from the object S that passes through the detection area provided between the light-emitting element 34 and a light-receiving element 35, so as to enter the light-receiving element 35. In other words, the pulse light for entering the light-receiving element 35 is set ON and OFF in response to the passing of the object S.
An optical signal, which is an output of the light-receiving element 35, is subjected to amplification and waveform shaping by an amplifier 36, and is then sent to a decision circuit 37. The output of the decision circuit 37 is sent to a signal processing circuit 32.
As shown in FIG. 5, the signal processing circuit 2 is composed of (a) R-S flip-flops 43 and 44, respectively attached with a timing gate, for capturing data at output detecting points A and B of the decision circuit 37 and for holding the data (hereinafter simply referred to as R-S flip-flops 43 and 44), (b) a shift register 41, which is arranged to feedback an inversion signal from serial output to serial input so as to shift the supplied input data in accordance with clock pulse having a predetermined cycle, and (c) a state detecting circuit 42. The state detecting circuit 42 is composed of (a) AND gates 45 and 46 for controlling the shift register 41 to be set and reset in response to (1) output of the shift register 41 (an output signal from an inverting output terminal /Q2 of a D flip-flop 41c as later described), (2) the clock pulse, and (3) a signal from output terminals (Q, /Q) of the R-S flip-flop 43 which holds the data captured at the detecting point B, and (b) an NAND gate 47, supplied with (1) output of the R-S flip-flop 44 which holds the data captured at the detecting point A and (2) the clock pulse, for controlling supply of the clock pulse into the shift register 41.
More specifically, an output terminal Q0 of the D flip-flop 41a is connected to a data input terminal D1 of the D flip-flop 41b, and an output terminal Q1 of the D flip-flop 41b is connected to a data input terminal D2 of the D flip-flop 41c. The inverting output terminal /Q2 of the D flip-flop 41c is connected to a data input terminal D0 of the D flip-flop 41a. Further, reset terminals R0 through R2 of the D flip-flops 41a through 41c are respectively connected to an output terminal of the AND gate 46 as later described. Set terminals S0 through S2 of the D flip-flops 41a through 41c are respectively connected to an output terminal of the AND gate 45 as later described. Clock input terminals CLK0 through CLK2 of the D flip-flops 41a through 41c are respectively connected to an output terminal of the NAND gate 47 as later described.
The signal processing circuit 32 is further provided with the state detecting circuit 42. The state detecting circuit 42 is composed of the AND gates 45 and 46, an inverter gate 48, and three NAND gates 47, 49, and 50 (respectively having two inputs).
The output signal of the inverting output terminal /Q2 of the D flip-flop 41c is sent to an input terminal (first input terminal) of the AND gate 45 via the inverter gate 48. The inverting output terminal /Q2 of the D flip-flop 41c is also connected to an input terminal (first input terminal) of the AND gate 46. The clock pulse is respectively supplied to input terminals (second input terminals) of the AND gates 45 and 46. An output terminal of the NAND gate 49 is connected to the remaining input terminal (third input terminal) of the AND gate 46, whereas an output terminal of the NAND gate 50 is connected to the remaining input terminal (third input terminal) of the AND gate 45.
An input terminal of the NAND gate 47 is applied with the clock pulse that varies in accordance with the output of the oscillation circuit 31. Another input terminal of the NAND gate 47 is connected to the inverting output terminal /Q of the R-S flip-flop 44.
The NAND gate 50 has one input terminal connected to the inverting output terminal /Q of the R-S flip-flop 44, and another input terminal connected to the inverting output terminal /Q of the R-S flip-flop 43. Further, the NAND gate 49 has one input terminal connected to the output terminal Q of the R-S flip-flop 43, and another input terminal connected to the inverting output terminal /Q of the R-S flip-flop 44.
According to the above-described circuit configuration, when the output of the decision circuit 37 (receiving signal) is at the high level at the detecting point A (non-light-emitting timing) (i.e., the disturbance light noise exists), the R-S flip-flop 44 is set, so that the inverting output terminal /Q of the R-S flip-flop 44 constantly supplies a low-level signal to the input terminal of the NAND gate 47. Accordingly, irrespectively of the clock pulse, the output terminal of the NAND gate 47 constantly supplies a high-level signal to the respective clock input terminals CLK0 through CLK2 of the D flip-flops 41a through 41c, so that the shift register 41 does not perform shifting operations.
On the other hand, when the output of the decision circuit 37 (receiving signal) is at the high level at the detecting point B (light-emitting timing), the R-S flip-flop 43 is set, so that the inverting output terminal /Q of the R-S flip-flop 43 turns to be at the low level and the output terminal Q of the R-S flip-flop 43 turns to be at the high level. Here, the R-S flip-flop 44 is reset so that the inverting output terminal /Q of the R-S flip-flop 44 turns to be at the high level. As a result, the input terminals of the NAND gate 50 respectively receive the low-level signal from the R-S flip-flop 43 and the high-level signal from the R-S flip-flop 44. Consequently, the output terminal of the NAND gate 50 outputs a high-level signal to the input terminal of the AND gate 45.
Since the output terminal Q of the R-S flip-flop 43 is at the high level, the output of the NAND gate 49 turns to be at the low level. As a result, the low-level signal is supplied to the input terminal of the AND gate 46. Here, when the inverting output terminal /Q2 of the D flip-flop 41c in the shift register 41 outputs the low-level signal, the output of the AND gate 45 turns to be at the high level. Accordingly, the high-level signal is supplied to the respective set input terminals of the D flip-flops 41a through 41c of the shift register 41, so as to set all bits of the D flip-flops 41a through 41c to be at the high level.
In contrast, when the output of the decision circuit 37 (receiving signal) is at the low level at the detecting point B (light-emitting timing), the R-S flip-flops 43 and 44 are reset, so that the inverting output terminals /Q of the R-S flip-flops 43 and 44 turn to be at the high level. As a result, the output (low level) of the NAND gate 50 is supplied to the input terminal of the AND gate 45, so as to turn the output of the AND gate 45 to be at the low level. Here, the output terminal of the AND gate 49 supplies the high-level signal to the input terminal of the AND gate 46.
Under this condition, when the inverting output terminal /Q2 of the D flip-flop 41c in the shift register 41 continues to output the low-level signal, the output of the AND gate 46 turns to be at the low level, and the NAND gate 47 supplies the clock pulse to the respective clock input terminals CLK0 through CLK2 of the D flip-flops 41a through 41c. As a result, the low-level signal is respectively supplied to the set input terminals and the reset input terminals of the shift register 41, so that the shift register 41 performs shifting operations. Namely, in synchronism with the clock pulse, the data are shifted per bit at the respective input terminals of the D flip-flops 41a through 41c. When the output of the decision circuit 37 (receiving signal) continues to be at the low level for the number of cascade stages of the D flip-flop in the shift register 41, the output of the shift register 41 (the signal of the output terminal Q2 of the D flip-flop 41c) is inverted.
On the other hand, when the inverting output terminal /Q2 of the D flip-flop 41c in the shift register 41 outputs the high-level signal under the above-described condition wherein the output of the decision circuit 37 (receiving signal) is at the low level at the detecting point B (light-emitting timing), the R-S flip-flops 43 and 44 are reset. Accordingly, the output terminals Q of the R-S flip-flops 43 and 44 respectively output the low-level signal, and the inverting output terminals /Q of the R-S flip-flops 43 and 44 respectively output the high-level signal.
As a result, the low-level signal from the R-S flip-flop 43 and the high-level signal from the R-S flip-flop 44 are respectively supplied to the input terminals of the NAND gate 49. Consequently, the output terminal of the NAND gate 49 supplies the high-level signal to the AND gate 46. Further, in this case, the inverting output terminal /Q2 of the D flip-flop 41c outputs the high-level signal, so that this high-level signal and the high-level signal from the output terminal of the NAND gate 49 are respectively supplied to the input terminals of the AND gate 46. As described above, the output terminal of the AND gate 46 supplies the high-level signal to the respective reset terminals of the D flip-flops 41a through 41c while the clock pulse is at the high level, so that the D flip-flops 41a through 41c are respectively reset. In other words, all bits of the shift register 41 are reset, so that the output terminals Q0 through Q2 of the D flip-flops 41a through 41c respectively output the low-level signal.
However, in this case, when the output of the decision circuit 37 (receiving signal) at the detecting point B is at the low level, the output terminals of the AND gates 45 and 46 output the low-level signal to the respective set input terminals (S0 through S2) of the D flip-flops 41a through 41c and to the respective reset input terminals (R0 through R2) of the D flip-flops 41a through 41c, respectively. This allows the shift register 41 to perform shifting operations, so that the signals are respectively shifted per bit at the respective output terminals (Q0 through Q2) of the D flip-flops 41a through 41c in synchronism with the clock pulse. When this state continues for the number of cascade stages of the D flip-flop that compose the shift register 41 (three stages in FIG. 5), the output terminal Q2 of the D flip-flop 41c is inverted from the low level to the high level.
As shown in FIG. 6, in the oscillation circuit 31, while the condenser C11 is not charged, [a potential of an inverting input terminal] is smaller than [a potential of a non-inverting input terminal] at a comparator 31a, so that the comparator 31a outputs a high-level signal. Consequently, transistors QN16, QN17, and QN18 are switched ON, so as to switch OFF transistors QN14 and QN15. Accordingly, the condenser C11 is charged with constant current I12 which is supplied from a transistor QP16, so that the potential of the inverting input terminal of the comparator 31a increases. When the voltage of the inverting input terminal exceeds (V2+V3) (V2 and V3 indicate voltages at both ends of resistances R11 and R13, respectively), the output of the comparator 31a is inverted from the high level to a low level. Consequently, the transistors QN16, QN17, and QN18 are switched OFF, so as to switch ON the transistors QN14 and QN15. Accordingly, since an emitter area ratio of the transistors QN14 and QN15 is set as 1:2, the transistor QN15 respectively extracts I12 from the transistor QP16 and from the condenser C1. Namely, when the potential of the inverting input terminal of the comparator 31a becomes lower than the potential of the non-inverting input terminal of the comparator 31a (=V2+Vsat (QN19), where Vsat (QN19) is a saturation voltage of the transistor QN19 whose value is not more than 0.1 [V]), the output of the comparator 31a is inverted again from the low level to the high level so as to charge the condenser C11. By repeating the above-described operations, the oscillation circuit oscillates with a cycle wherein the condenser C11 is charged and discharged.
According to the above-described conventional technique, however, the detection signal from the light-receiving element 35 is processed in synchronism with the pulse-modulated light emitted from the light-emitting element 34. Accordingly, while the light-emitting element 34 does not emit light, the detection signal from the light-receiving element 35 is not demodulated with the synchronizing signal, but is discarded.
While the light-emitting element 34 does not emit the pulse-modulated light, when noise occurs or disturbance light enters the light-receiving element 35 in synchronism with the synchronizing signal, even the demodulation with the synchronizing signal cannot completely eliminate the disturbance light and the noise. This may cause the light-receiving element 35 to misjudge that the pulse-modulated light that is emitted from the light-emitting element 34 is entering the light-receiving element 35, thereby resulting in faulty operation.
More specifically, the detecting point A (light-emitting timing) is prepared for detecting disturbance light noise. In case where light enters in synchronism with timing other than the pulse-modulated frequency (non-light-emitting timing), the R-S flip-flop 44 is set when the output of the decision circuit 37 (light-receiving signal) is at the high level at the detecting point A, so that the inverting output terminal /Q outputs a low-level signal. This switches OFF the AND gate 47 so as not to supply the clock pulse to the shift register 41.
While the light-emitting element 34 does not emit pulse-modulated light, however, when the light that corresponds to not less than the number of stages of the shift register 41 enters the light-receiving element 35 for some reason (accidentally or intentionally) in synchronism with the timing of the pulse-modulated frequency (light-emitting timing), the inverting output terminal (/Q2) at the last stage of the shift register 41 is inverted, thereby resulting in faulty detection.